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ks07 59 81 com / 1 28 seg drive r & controller for stn lcd aug ust. 1999. ver. 0 . 2 prepared by hyun-oh,lee exprss@samsung.co.kr contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 2 ks07 59 specification revision history version content date 0.0 original july.1999 0.1 remove hpmb, cs2 pin and change vol, voh value july.1999 0.2 modify pad dimensions and chip configuration aug.1999
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 3 co ntents introduction ................................ ................................ ................................ ................................ .................. 1 block diagram ................................ ................................ ................................ ................................ ............... 2 pad configuration ................................ ................................ ................................ ................................ ....... 3 pin description ................................ ................................ ................................ ................................ .............. 7 power supply ................................ ................................ ................................ ................................ .......... 7 lcd driver supply ................................ ................................ ................................ ................................ .. 7 system control ................................ ................................ ................................ ................................ ..... 8 microprocessor interface ................................ ................................ ................................ ............... 9 lcd driver outputs ................................ ................................ ................................ ............................. 11 functional description ................................ ................................ ................................ ............................ 12 microprocessor interface ................................ ................................ ................................ ............. 12 display data ram (ddram) ................................ ................................ ................................ .................. 16 lcd display circuits ................................ ................................ ................................ ............................ 20 lcd driver circuit ................................ ................................ ................................ ............................... 22 power supply circuits ................................ ................................ ................................ ...................... 25 referece circuit examples ................................ ................................ ................................ .............. 30 reset circuit ................................ ................................ ................................ ................................ ......... 32 instruction description ................................ ................................ ................................ ........................... 33 specifications ................................ ................................ ................................ ................................ .............. 53 absolute maximum ratings ................................ ................................ ................................ ............... 53 dc characteristics ................................ ................................ ................................ ............................. 54 ac characteristics ................................ ................................ ................................ ............................. 57 reference applications ................................ ................................ ................................ ........................... 61 microprocessor interface ................................ ................................ ................................ ............. 61 connections between KS0759 and lcd panel ................................ ................................ .............. 63

ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 1 introduction the ks07 59 is a driver & controller lsi for graphic dot-matrix liquid crystal display systems. it contains 81 common and 1 28 segment driver circuits. this chip is connected directly to a microprocessor, accepts serial or 8- bit parallel display data and stores in an on-chip display data ram of 8 1 x 1 28 bits. it provides a highly flexible display section due to 1-to-1 correspondence between on-chip display data ram bits and lcd panel pixels. and it performs display data ram read/write operation with no external ly operating clock to minimize power consumption. in addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. features driver output circuits - 81 common outputs / 1 28 segment outputs applicable duty ratios programmable duty ratio applicable lcd bias maximum display area 1/ 17 to 1/81 1/4 to 1/11 81 1 28 - various partial display - partial window moving & data scrolling on-chip display data ram - capacity: 8 1 x 128 = 10 , 368 bits - bit data "1": a dot of display is illuminated . - bit data "0": a dot of display is not illuminated . microprocessor interface - 8-bit parallel bi-directional interface with 6800-series or 8080-series . - spi ( serial peripheral i nterface ) available . (only write operation) on-chip low power analog circuit - on-chip oscillator circuit - voltage converter (x3, x4, x5 or x6) - voltage regulator (temperature coefficient: -0.05%/ c or external input) - on-chip electronic contrast control function (64 steps) - voltage follower (lcd bias: 1/4 to 1/11) operating voltage range - supply voltage (v dd ): 1 . 8 to 3 . 3 v - lcd driving voltage (v lcd = v0 - v ss ): 4.0 to 1 5 .0 v low power consumption - tbd m a typ. ( i nternal power supply on and display off) package type - gold bump chip or tcp
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 2 block diagram internal p ower supply vdd v0 v1 v2 v3 v4 vss v0 vr intrs vext ref vout c1- c1+ c2- c2+ c3+ c4+ c5+ vci v / c circuit v / r c ircuit v / f circuit 8 2 common driver circuits mpu interface (parallel & serial) instruction decoder & register status register bus holder column address circuit line address circuit page address circuit display data ram 81 x 128 = 10,368bits segment controller display timing generator circuit / oscillator common controller db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) rw_wr e_rd rs cs1b ps 0 ps1 resetb coms 1 com 79 : : : com0 coms seg 127 seg126 seg125 : : seg2 seg1 seg0 1 28 segment d river circuits test1 test2 test3 test4 figure 1 . block diagram
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 3 pad configuration 15 5 312 . . . . . . . . . . . . . . . x y (0,0) ks0 759 (top view ,pad up) 1 123 124 154 313 343 normal pad dummy pad . . . . . . . . . . . . . . . . . . . . . .... figure 2 . ks07 59 chip configuration table 1. KS0759 pad dimension [ [ dummy to dummy pad pitch is 80 um . dummy to n ormal p ad pitch is 70 um. item pad no. size unit x y chip size - 9 9 8 0 2 3 8 0 um pad pitch input 1 to 1 2 3 7 0 output 1 2 5 to 1 5 2 6 0 1 5 7 to 3 1 0 3 1 5 to 3 4 2 nc* 1 2 4 , 3 4 3 7 0 1 5 4 , 1 5 5 , 3 1 2 , 3 1 3 8 0 1 5 3 , 1 5 6 , 3 1 1 , 3 1 4 7 0 / 8 0 bumped pad size ( max.) 1 to 1 2 3 5 0 1 0 0 1 2 4 1 1 0 6 0 1 2 5 to 1 5 2 1 1 0 4 0 1 5 3 to 1 5 4 1 1 0 6 0 1 5 5 to 1 5 6 6 0 1 1 0 1 5 7 to 3 1 0 4 0 1 1 0 3 1 1 to 3 1 2 6 0 1 1 0 3 1 3 to 3 1 4 1 1 0 6 0 3 1 5 to 3 4 2 1 1 0 4 0 3 4 3 1 1 0 6 0 bumped pad height all pad 1 4 ( typ.)
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 4 cog align key coordinate ilb align key coordinate 42 m 108 m 30 m m 30 m m 30 m m (+ 4265 , +465 ) 30 m 30 m 30 m (- 4310 , -510 ) 30 m m 30 m m 30 m m 30 m 30 m 30 m (+ 4265 , +375 ) 108 m m 42 m m 42 m 108 m ( 4310 , 510 ) 108 m m
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 5 pad center coordinates table 1 . p ad center coordinates [unit: m m] no. name x y no. name x y no. name x y no. name x y 1 pad_ck -4270 -1075 51 vss -770 -1075 101 v4 2730 -1075 151 com13 4843 650 2 test_cl -4200 -1075 52 vss -700 -1075 102 v4 2800 -1075 152 com12 4843 710 3 scl -4130 -1075 53 vss -630 -1075 103 v4 2870 -1075 153 dummy 4843 780 4 sda -4060 -1075 54 vout -560 -1075 104 v3 2940 -1075 154 dummy 4843 860 5 vss -3990 -1075 55 vout -490 -1075 105 v3 3010 -1075 155 dummy 4740 1043 6 vdd -3920 -1075 56 vout -420 -1075 106 v3 3080 -1075 156 dummy 4660 1043 7 vdd -3850 -1075 57 vout -350 -1075 107 v3 3150 -1075 157 com11 4590 1043 8 ps0 -3780 -1075 58 vout -280 -1075 108 v2 3220 -1075 158 com10 4530 1043 9 vss -3710 -1075 59 vout -210 -1075 109 v2 3290 -1075 159 com9 4470 1043 10 vdd -3640 -1075 60 vout -140 -1075 110 v2 3360 -1075 160 com8 4410 1043 11 ps1 -3570 -1075 61 vout -70 -1075 111 v2 3430 -1075 161 com7 4350 1043 12 vss -3500 -1075 62 c5+ 0 -1075 112 v1 3500 -1075 162 com6 4290 1043 13 cs1b -3430 -1075 63 c5+ 70 -1075 113 v1 3570 -1075 163 com5 4230 1043 14 vdd -3360 -1075 64 c5+ 140 -1075 114 v1 3640 -1075 164 com4 4170 1043 15 vdd -3290 -1075 65 c5+ 210 -1075 115 v1 3710 -1075 165 com3 4110 1043 16 resetb -3220 -1075 66 c3+ 280 -1075 116 v0 3780 -1075 166 com2 4050 1043 17 rs -3150 -1075 67 c3+ 350 -1075 117 v0 3850 -1075 167 com1 3990 1043 18 vss -3080 -1075 68 c3+ 420 -1075 118 v0 3920 -1075 168 com0 3930 1043 19 rw_wr -3010 -1075 69 c3+ 490 -1075 119 v0 3990 -1075 169 coms 3870 1043 20 e_rd -2940 -1075 70 c1- 560 -1075 120 vr 4060 -1075 170 seg0 3810 1043 21 vdd -2870 -1075 71 c1- 630 -1075 121 vr 4130 -1075 171 seg1 3750 1043 22 db0 -2800 -1075 72 c1- 700 -1075 122 vss 4200 -1075 172 seg2 3690 1043 23 db1 -2730 -1075 73 c1- 770 -1075 123 vss 4270 -1075 173 seg3 3630 1043 24 db2 -2660 -1075 74 c1- 840 -1075 124 dummy 4843 -980 174 seg4 3570 1043 25 db3 -2590 -1075 75 c1- 910 -1075 125 com39 4843 -910 175 seg5 3510 1043 26 db4 -2520 -1075 76 c1+ 980 -1075 126 com38 4843 -850 176 seg6 3450 1043 27 db5 -2450 -1075 77 c1+ 1050 -1075 127 com37 4843 -790 177 seg7 3390 1043 28 db6 -2380 -1075 78 c1+ 1120 -1075 128 com36 4843 -730 178 seg8 3330 1043 29 db7 -2310 -1075 79 c1+ 1190 -1075 129 com35 4843 -670 179 seg9 3270 1043 30 vdd -2240 -1075 80 c2+ 1260 -1075 130 com34 4843 -610 180 seg10 3210 1043 31 vdd -2170 -1075 81 c2+ 1330 -1075 131 com33 4843 -550 181 seg11 3150 1043 32 vdd -2100 -1075 82 c2+ 1400 -1075 132 com32 4843 -490 182 seg12 3090 1043 33 vdd -2030 -1075 83 c2+ 1470 -1075 133 com31 4843 -430 183 seg13 3030 1043 34 vdd -1960 -1075 84 c2- 1540 -1075 134 com30 4843 -370 184 seg14 2970 1043 35 vdd -1890 -1075 85 c2- 1610 -1075 135 com29 4843 -310 185 seg15 2910 1043 36 vci -1820 -1075 86 c2- 1680 -1075 136 com28 4843 -250 186 seg16 2850 1043 37 vci -1750 -1075 87 c2- 1750 -1075 137 com27 4843 -190 187 seg17 2790 1043 38 vci -1680 -1075 88 c2- 1820 -1075 138 com26 4843 -130 188 seg18 2730 1043 39 vci -1610 -1075 89 c2- 1890 -1075 139 com25 4843 -70 189 seg19 2670 1043 40 vci -1540 -1075 90 c4+ 1960 -1075 140 com24 4843 -10 190 seg20 2610 1043 41 vci -1470 -1075 91 c4+ 2030 -1075 141 com23 4843 50 191 seg21 2550 1043 42 vci -1400 -1075 92 c4+ 2100 -1075 142 com22 4843 110 192 seg22 2490 1043 43 vci -1330 -1075 93 c4+ 2170 -1075 143 com21 4843 170 193 seg23 2430 1043 44 vss -1260 -1075 94 vss 2240 -1075 144 com20 4843 230 194 seg24 2370 1043 45 vss -1190 -1075 95 ref 2310 -1075 145 com19 4843 290 195 seg25 2310 1043 46 vss -1120 -1075 96 vext 2380 -1075 146 com18 4843 350 196 seg26 2250 1043 47 vss -1050 -1075 97 vdd 2450 -1075 147 com17 4843 410 197 seg27 2190 1043 48 vss -980 -1075 98 intrs 2520 -1075 148 com16 4843 470 198 seg28 2130 1043 49 vss -910 -1075 99 vss 2590 -1075 149 com15 4843 530 199 seg29 2070 1043 50 vss -840 -1075 100 v4 2660 -1075 150 com14 4843 590 200 seg30 2010 1043
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 6 table 2 . p ad center coordinates (continued) [ u nit: m m] no. name x y no. name x y no. name x y no. name x y 201 seg31 1950 1043 251 seg81 -1050 1043 301 com43 -4050 1043 202 seg32 1890 1043 252 seg82 -1110 1043 302 com44 -4110 1043 203 seg33 1830 1043 253 seg83 -1170 1043 303 com45 -4170 1043 204 seg34 1770 1043 254 seg84 -1230 1043 304 com46 -4230 1043 205 seg35 1710 1043 255 seg85 -1290 1043 305 com47 -4290 1043 206 seg36 1650 1043 256 seg86 -1350 1043 306 com48 -4350 1043 207 seg37 1590 1043 257 seg87 -1410 1043 307 com49 -4410 1043 208 seg38 1530 1043 258 seg88 -1470 1043 308 com50 -4470 1043 209 seg39 1470 1043 259 seg89 -1530 1043 309 com51 -4530 1043 210 seg40 1410 1043 260 seg90 -1590 1043 310 com52 -4590 1043 211 seg41 1350 1043 261 seg91 -1650 1043 311 dummy -4660 1043 212 seg42 1290 1043 262 seg92 -1710 1043 312 dummy -4740 1043 213 seg43 1230 1043 263 seg93 -1770 1043 313 dummy -4843 860 214 seg44 1170 1043 264 seg94 -1830 1043 314 dummy -4843 780 215 seg45 1110 1043 265 seg95 -1890 1043 315 com53 -4843 710 216 seg46 1050 1043 266 seg96 -1950 1043 316 com54 -4843 650 217 seg47 990 1043 267 seg97 -2010 1043 317 com55 -4843 590 218 seg48 930 1043 268 seg98 -2070 1043 318 com56 -4843 530 219 seg49 870 1043 269 seg99 -2130 1043 319 com57 -4843 470 220 seg50 810 1043 270 seg100 -2190 1043 320 com58 -4843 410 221 seg51 750 1043 271 seg101 -2250 1043 321 com59 -4843 350 222 seg52 690 1043 272 seg102 -2310 1043 322 com60 -4843 290 223 seg53 630 1043 273 seg103 -2370 1043 323 com61 -4843 230 224 seg54 570 1043 274 seg104 -2430 1043 324 com62 -4843 170 225 seg55 510 1043 275 seg105 -2490 1043 325 com63 -4843 110 226 seg56 450 1043 276 seg106 -2550 1043 326 com64 -4843 50 227 seg57 390 1043 277 seg107 -2610 1043 327 com65 -4843 -10 228 seg58 330 1043 278 seg108 -2670 1043 328 com66 -4843 -70 229 seg59 270 1043 279 seg109 -2730 1043 329 com67 -4843 -130 230 seg60 210 1043 280 seg110 -2790 1043 330 com68 -4843 -190 231 seg61 150 1043 281 seg111 -2850 1043 331 com69 -4843 -250 232 seg62 90 1043 282 seg112 -2910 1043 332 com70 -4843 -310 233 seg63 30 1043 283 seg113 -2970 1043 333 com71 -4843 -370 234 seg64 -30 1043 284 seg114 -3030 1043 334 com72 -4843 -430 235 seg65 -90 1043 285 seg115 -3090 1043 335 com73 -4843 -490 236 seg66 -150 1043 286 seg116 -3150 1043 336 com74 -4843 -550 237 seg67 -210 1043 287 seg117 -3210 1043 337 com75 -4843 -610 238 seg68 -270 1043 288 seg118 -3270 1043 338 com76 -4843 -670 239 seg69 -330 1043 289 seg119 -3330 1043 339 com77 -4843 -730 240 seg70 -390 1043 290 seg120 -3390 1043 340 com78 -4843 -790 241 seg71 -450 1043 291 seg121 -3450 1043 341 com79 -4843 -850 242 seg72 -510 1043 292 seg122 -3510 1043 342 coms1 -4843 -910 243 seg73 -570 1043 293 seg123 -3570 1043 343 dummy -4843 -980 244 seg74 -630 1043 294 seg124 -3630 1043 245 seg75 -690 1043 295 seg125 -3690 1043 246 seg76 -750 1043 296 seg126 -3750 1043 247 seg77 -810 1043 297 seg127 -3810 1043 248 seg78 -870 1043 298 com40 -3870 1043 249 seg79 -930 1043 299 com41 -3930 1043 250 seg80 -990 1043 300 com42 -3990 1043
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 7 pin description power supply table 2 . power supply p ins name i/o description vdd supply power supply v ss supply ground lcd driver suppl ies voltages the voltage determined by lcd pixel is impedance converted by an operational amplifier for application. voltages should have the following relation ship ; v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the internal power circuit is active, these voltages are generated as following table according to the state of lcd b ias. lcd bias v1 v2 v3 v4 1/n bias (n-1) / n x v0 (n-2) / n x v0 ( 2/n ) x v0 ( 1/n ) x v0 v0 v1 v2 v3 v4 i/o note: n = 4 to 11 lcd driver supply table 3 . lcd driver supply p ins name i/o description c1- o capacitor 1 negative connection pin for voltage converter c1+ o capacitor 1 positive connection pin for voltage converter c2- o capacitor 2 negative connection pin for voltage converter c2+ o capacitor 2 positive connection pin for voltage converter c3+ o capacitor 3 positive connection pin for voltage converter c4+ o capacitor 4 positive connection pin for voltage converter c5+ o capacitor 5 positive connection pin for voltage converter vout i/o voltage converter input / output pin vci i voltage converter input voltage pin voltages should have the following relationship: vdd vci v0 vr i v0 voltage adjustment pin it is valid only when on-chip resistors are not used (intrs = "l") ref i selects the external vref voltage via vext pin - ref = "l": using the external vref - ref = "h": using the internal vref vext i externally input reference voltage (vref) for the internal voltage regulator it is valid only when ref is "l".
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 8 system control table 4 . system control p ins name i/o description intrs i internal resistors select pin this pin selects the resistors for adjusting v0 voltage level. - intrs = "h": use the internal resistors - intrs = "l": use the external resistors vr pin and external resistive divider control v0 voltage . test1 to test 4 i test pins don?t use these pins.
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 9 microprocessor interface table 5 . microprocessor i nterface p ins name i/o description resetb i reset the input pin when resetb is "l", initialization is executed. parallel/serial data input select input ps 0 interface mode data/ instruction data read / write serial clock h parallel rs db0 to db7 e_rd rw_wr - l serial rs or none sid(db7) write only sclk(db6) ps 0 i *note: when ps is "l", db0 to db5 are high impedance and e_rd and rw_wr must be fixed to either "h" or "l". ps1 i microprocessor interface select input pin - ps0 = ? h ? , ps1 = "h": 6800-series parallel mpu interface - ps0 = ? h ? , ps1 = "l": 8080-series parallel mpu interface - ps0 = ? l ? , ps1 = "h": 4 pin-spi serial mpu interface - ps0 = ? l ? , ps1 = "l": 3 pin-spi serial mpu interface cs1b i chip select input pins data/instruction i/o is enabled only when cs1b is "l" . when chip select is non-active, db0 to db7 may be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a - rs = "l": db0 to db7 are control data read / write execution control pin ps1 mpu type rw_wr description h 6800-series rw read/write control input pin - rw = "h": r ead - rw = "l": w rite l 8080-series /wr write enable clock input pin the data on db0 to db7 are latched at the rising edge of the /wr signal. rw_wr i
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 10 table 6 (continued) name i/o description read / write execution control pin ps1 mpu type e_rd description h 6800-series e read/write control input pin - rw = "h": when e is "h", db0 to db7 are in an output status. - rw = "l": the data on db0 to db7 are latched at the falling edge of the e signal. l 8080-series /rd read enable clock input pin when /rd is "l", db0 to db7 are in an output status. e_rd i db0 to db7 i/o 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. when the serial interface selected (ps 0 = "l"); - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: serial input data (sid) when chip select is not active, db0 to db7 may be high impedance.
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 11 lcd driver outputs table 6 . lcd d river o utputs p ins name i/o description lcd segment driver outputs the display data and the m signal control the output voltage of segment driver. segment driver output voltage display data m (internal) normal display reverse display h h v0 v2 h l v ss v3 l h v2 v0 l l v3 v ss power save mode v ss v ss seg0 to seg1 27 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data m (internal) common driver output voltage h h v ss h l v0 l h v1 l l v4 power save mode v ss com0 to com79 o coms (coms1) o common output for the icons the output signals of two pins are same. when not used, these pins should be left open. note: dummy ? these pins should be opened (floated).
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 12 functional description microprocessor interface chip select input there are cs1b for chip selection. the ks07 59 can interface with an mpu only when cs1b is "l" . when these pins are set to any other combination, rs, e_rd, and rw_wr inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface ks07 59 has four types of interface with an mpu, which are two serial and two parallel interface. this parallel or serial interface is determined by ps 0 pin as shown in table 7 . table 7 . parallel / serial interface mode ps 0 type cs1b ps1 interface mode h 6800-series mpu mode h parallel cs1b l 8080-series mpu mode h 4 pin-spi mpu mode l serial cs1b l 3 pin-spi mpu mode parallel interface (ps 0 = "h") the 8-bit bi-directional data bus is used in parallel interface and the type of mpu is selected by ps1 as shown in table 8 . the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 9 . table 8 . microprocessor selection for parallel interface ps1 cs1b rs e_rd rw_wr db0 to db7 mpu bus h cs1b rs e rw db0 to db7 6800-series l cs1b rs /rd /wr db0 to db7 8080-series table 9 . parallel data transfer common 6800-series 8080-series description rs e_rd (e) rw_wr (rw) e_rd (/rd) rw_wr (/wr) h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction)
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 13 serial interface (ps 0 = "l") when the KS0759 is active (cs1b= ? l ? ) , serial data (db7) and serial clock (db6) inputs are enabled. and not active, the internal 8-bit shift register and the 3-bit counter are reset. the display data/command indication may be controlled either via software or the register select(rs) pin, based on the setting of ps1. when the rs pin is used (ps1 = ? h ? ), data is display data when rs is high, and command data when rs is low. when rs is not used (ps1 = ? l ? ), the lcd driver will receive command from mpu by default. if messages on the data pin are data rather than command, m p u should send data direction command(111 0 1000) to control the data direction and then one more command to define the number of data bytes will be write. after these two continuous commands are send, the following messages will be data rather than command. serial data can be read on the rising edge of serial clock going into db6 and processed as 8-bit parallel data on the eighth serial clock. and the ddram column address pointer will be increased by one automatically. the next bytes after the display data string is handled as command data. serial mode ps0 ps1 cs1b rs serial-mode with rs pin l h cs1b used serial-mode with software command l l cs1b not used 4 pin-spi interface (ps 0 = "l" , ps1 = " h ") cs1b sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 3 . 4 pin spi timing (rs is used)
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 14 3 pin-spi interface (ps 0 = "l" , ps1 = " l ") to write data to the ddram, send data direction command in 3-pin spi mode. data is latched at the rising edge of s clk. and the ddram column address pointer will be increased by one automatically. sclk cs1b 829 830 831 ~ ~ ~ ~ 0 0 1 7 8 ~ ~ 15 ~ ~ 23 sid msb data in page lsb ddc no. of data 3 byte (1) 2 byte (2) 128 byte 0 (1) set page and column address. set page address : 1 0 1 1 p3 p2 p1 p0 set column address msb : 0 0 0 1 0 y6 y5 y4 set column address lsb : 0 0 0 0 y3 y2 y1 y0 (2) set ddc(data direction command) and no. of data bytes. set data direction command( for spi mode only): 1 1 1 0 1 0 0 0 set no. of data bytes(ddl) : d7 d6 d5 d4 d3d2d1d0 figure 4 . 3 pin spi timing (rs is not used) this command is used in 3-pin spi mode only. it will be two continuous commands, the first byte control s the data direction and inform s the lcd driver the second byte will be number of data bytes will be write. after these two commands sending out, the following messages will be data. if data is stopped in transmitting, i t i s not valid data. new d ata will be transferred serially with most significant bit first. notes: l in spite of transmission of d ata, if cs1b will be disable, state terminates abnormally. next state is initialized. l ddl register value ? 0 ? ? 1 ? , ? 127 ? ? 128 ? . (decimal value) busy flag the b usy f lag indicates whether the ks07 59 is operating or not. when db7 is "h" in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance.
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 15 data transfer the ks07 59 uses bus holder and internal data bus for d ata t ransfer with the mpu. when writing data from the mpu to on-chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 5 . and when reading data from on-chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 6 . this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. t herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. rs /wr db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 5 . write timing rs /wr /rd db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals /wr /rd bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 figure 6 . read timing
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 16 display data ram (ddram) the display data ram stores pixel data for the lcd. it is 8 1 -row by 1 28 -column addressable array. each pixel can be selected when the page and column addresses are specified. the 8 1 rows are divided into 1 0 pages of 8 lines and the 1 1 th page with a single line (db0 only). data is read from or written to the 8 lines of each page directly t hrough db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 7 . the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. com0 - - com1 - - com2 - - com3 - - com4 - - db0 0 0 1 - - 0 db1 1 0 0 - - 1 db2 0 1 1 - - 0 db3 1 0 1 - - 0 db4 0 0 0 - - 1 d isplay data ram lcd display figure 7 . ram-to-lcd data transfer page address circuit this circuit is for providing a p age a ddress to display data ram shown in figure 9 . it incorporates 4-bit p age a ddress register changed by only the "set page" instruction. page a ddress 1 0 (db3 and db1 are " h " , db2 and db0 is "l") is a special ram area for the icons and display data db0 is only valid. line address circuit this circuit assigns ddram a l ine a ddress corresponding to the first line (com0) of the display. therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip ram as shown in figure 9 & figure 10 . it incorporates 7-bit l ine a ddress register changed by only the i nitial d isplay l ine instruction and 7-bit counter circuit. at the beginning of each lcd frame, the contents of register are copied to the line counter which is increased by cl signal and generates the l ine ad dress for transferring the 128-bit ram data to the display data latch circuit. however, display data of icons are not scrolled because the mpu can not access l ine a ddress of icons.
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 17 column address circuit column address circuit has a 7-bit preset counter that provides column address to the display data ram as shown in figure 9 . when set column address msb / lsb instruction is issued, 7-bit [y6:y0] is updated. and, since this address is increased by 1 each a r ead or w rite d ata instruction, microprocessor can access the display data continuously. and t he c olumn a ddress counter is independent of page address register. adc select instruction makes it possible to invert the relationship between the column address and the segment outputs. it is necessary to rewrite the display data on built-in ram after issuing adc select instruction. refer to the following figure 8 . seg output seg 0 seg 1 seg 2 seg 3 ... ... seg 124 seg 125 seg 126 seg 127 column address [y6:y0] 00h 01h 02h 03h ... ... 7c h 7d h 7e h 7f h display data 1 0 1 0 1 1 0 0 lcd panel display ( adc = 0 ) ... ... lcd panel display ( adc = 1 ) ... ... figure 8 . the relationship between the column address and the segment outputs segment control circuit this circuit controls the display data by the display on / off, reverse display on / off and entire display on / off instructions without changing the data in the display data ram.
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 18 page 0 page 2 page 1 page 3 page9 page 10 line address com output page address db3 db0 db1 db2 data seg127 seg126 seg1 seg0 seg125 seg124 seg123 seg122 seg2 seg3 seg4 seg5 - - - - - adc=1 adc=0 column address lcd output db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh com0 com9 com8 com7 com6 com5 com3 com4 com2 com1 com10 com19 com18 com17 com16 com15 com13 com14 com12 com11 com20 com29 com28 com27 com26 com25 com23 com24 com22 com21 com30 com67 com66 com65 com64 com63 com61 com62 com60 com31 com68 com77 com76 com75 com74 com73 com71 com72 com70 com69 com78 com79 coms page 8 page 7 page 9 40h 41h 42h 43h 44h 4ch 4bh 4ah 49h 48h 47h 46h 45h 4dh 4eh 4fh 1/73 duty 1/81 duty initial start line address = 00h 38h 39h 3ah 3bh 3ch 3fh 3eh 3dh com59 com57 com58 com56 00 - - - - - 01 02 03 04 05 7a 7b 7c 7d 7e 7f 00 - - - - - 01 02 03 04 05 7a 7b 7c 7d 7e 7f 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 initial line register = 00h figure 9 . display data ram map (initial l ine a ddress = 00h)
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 19 seg127 seg126 seg1 seg0 seg125 seg124 seg123 seg122 seg2 seg3 seg4 seg5 - - - - - adc=1 adc=0 column address lcd output initial start line address = 08h 00 - - - - - 01 02 03 04 05 7a 7b 7c 7d 7e 7f 00 - - - - - 01 02 03 04 05 7a 7b 7c 7d 7e 7f page 0 page 2 page 1 page 3 page9 page 10 line address page address db3 db0 db1 db2 data db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh page 8 page 7 page 9 40h 41h 42h 43h 44h 4ch 4bh 4ah 49h 48h 47h 46h 45h 4dh 4eh 4fh 38h 39h 3ah 3bh 3ch 3fh 3eh 3dh 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 com output com72 com1 com0 com79 com78 com77 com75 com76 com74 com73 com2 com11 com10 com9 com8 com7 com5 com6 com4 com3 com12 com21 com20 com19 com18 com17 com15 com16 com14 com13 com22 com59 com58 com57 com56 com55 com53 com54 com52 com23 com60 com69 com68 com67 com66 com65 com63 com64 com62 com61 com70 com71 coms com51 com49 com50 com48 1/73duty start = 08h end = 07h 1/81duty initial line register = 08h figure 10 . display data ram map (initial l ine a ddress = 08h)
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 20 lcd display circuits oscillator this is completely on-chip o scillator and its frequency is nearly independent of v dd . this o scillator signal is used in the voltage converter and display timing generation circuit. display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, cl (internal) , generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line address of on-chip ram is generated in synchronization with the display clock and the display data latch circuit latches the 1 28 -bit display data in synchronization with the display clock. the display data, which is read to the lcd driver, is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make a ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. the frame signal or the line signal changes the m by setting internal instruction. driving waveform and internal timing signal are shown in figure 11 .
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 21 fr(internal) m(internal) 80 81 1 2 3 4 5 6 7 8 9 10 11 12 74 75 76 77 78 79 80 81 1 2 3 4 5 6 cl(internal) com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn figure 11 . 2- f rame ac driving waveform ( d uty r atio = 1/81) com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn fr(internal) m(internal) 80 81 1 2 3 4 5 6 7 8 9 10 11 12 74 75 76 77 78 79 80 81 1 2 3 4 5 6 cl(internal) figure 12 . n-line inversion driving waveform (n = 5 , duty ratio = 1/81)
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 22 lcd driver circuit 8 1 -channel common driver and 1 28 -channel segment driver configure this driver circuit. this lcd panel driver voltage depends on the combination of display data and m signal. com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg2 seg1 seg0 com2 com0 com1 m v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss vdd vss figure 13 . segment and common timing
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 23 partial display on lcd the ks07 59 realizes the p artial d isplay function on lcd with low-duty driving for saving power consumption and showing the various display duty. to show the various display duty on lcd, lcd driving duty and bias are programmable via the instruction. and, built-in power supply circuits are controlled by the instruction for adjusting the lcd d riving voltages -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 14 . reference example for partial display (display duty = 25) -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 15 . partial display (partial display duty = 17 , initial com0 = 0)
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 24 -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 16 . moving display (partial display duty = 17 , initial com0 = 8 )
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 25 power supply circuits the p ower s upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low- power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and controlled by p ower c ontrol instruction. for details, refers to "instruction description". table 10 shows the referenced combinations in using p ower s upply circuits. table 10 . recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/r circuits v/f circuits vout v0 v1 to v4 only the internal power supply circuits are used 1 1 1 on on on open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on external input open open only the voltage follower circuits are used 0 0 1 off off on external input open open only the external power supply circuits are used 0 0 0 off off off open external input external input
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 26 voltage converter circuits these circuits boost up the electric potential between vci and vss to 3, 4, 5 or 6 times toward positive side and boosted voltage is outputted from vout pin. it is possible to select the lower boosting level in any boosting circuit by ?set dc-dc step-up? instruction. when the higher level is selected by instruction, vout voltage is not valid. [c1 = 1.0 to 4.7 m f] vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + vout = 3 x vci c1 - + c1 - + - vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + - c1 - + - vout = 4 x vci figure 17 . three times boosting circuit figure 18 . four times boosting circuit vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + - vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + - c1 - + - c1 - + - c1 - + c1 - + vout = 5 x vci vout = 6 x vci c1 - + - figure 19 . five times boosting circuit figure 20 . six times boosting circuit
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 27 voltage regulator circuits the function of the internal v oltage r egulator circuits is to determine liquid crystal operating voltage, v0, by adjusting resistors, ra and rb, within the range of |v0| < |vout|. because vout is the operating voltage of operational-amplifier circuits shown in figure 21 , it is necessary to be applied internally or externally. for the eq. 1, we determine v0 by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determined by eq. 2, where the parameter a is the value selected by instruction, "set reference voltage register", within the range 0 to 63. v ref voltage at ta= 25 c is shown in table 11 . rb v0 = (1 + ???? ) x v ev [v] ------ (eq. 1) ra (63 - a ) v ev = (1 - ?????? ) x v ref [v] ------ (eq. 2) 210 table 11 . . v ref voltage at ta = 25 c ref temp. coefficient v ref [ v ] 1 -0.05% / c 2.1 0 external input vext v ev gnd ra rb vss vr v0 vout + - figure 21 . internal voltage regulator circuit
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 28 in case of using internal resistors, ra and rb (intrs = "h?) when intrs pin is " h " , resistor ra is connected internally between vr pin and v ss , and rb is connected between v0 and vr. we determine v0 by two instructions, "regulator resistor select" and "set reference voltage". table 12 . internal rb / ra ratio depending on 3-bit data (r2 r1 r0) 3-bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb / ra) 2. 3 3. 0 3 . 7 4 . 4 5 . 1 5 . 8 6 . 5 7 . 2 figure 22 shows v0 voltage measured by adjusting internal regulator register ratio (rb / ra) and 6-bit electronic volume registers for each temperature coefficient at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 0 8 16 24 32 40 48 56 electronic volume register (0 to 63) v0 voltage [v] (1, 1, 1) 63 63 (1, 1, 0) (1, 0, 1) (1, 0 ,0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0) figure 22 . electronic volume level (temp. coefficient = -0.05% / c)
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 29 in case of using external resistors, ra and rb (intrs = "l") when intrs pin is " l " , it is necessary to connect external regulator resistor ra between vr and vss, and rb between v0 and vr. example: for the following requirements 1. lcd driver voltage, v0 = 10v 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. maximum current flowing ra, rb = 1 ua from eq. 1 rb 10 = (1 + ??? ) x v ev [v] ------ (eq. 3) ra from eq. 2 (63 - 32) v ev = (1 - ?????? ) x 2. 1 = 1. 7 9 [v] ------ (eq. 4) 2 1 0 from requirement 3. 10 ????? = 1 [ua] ------ (eq. 5) ra + rb from equations eq. 3, 4 and 5 ra = 1. 7 9 [m w ] rb = 8. 2 1 [m w ] table 13 shows the range of v0 depending on the above requirements. table 13 . the r ange of v0 electronic volume level 0 ....... 32 ....... 63 v0 8. 21 ....... 1 0 .00 ....... 11. 7 3 voltage follower circuits vlcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3 and v4), and those output impedance are converted by the v oltage f ollower for increasing drive capability. table 14 shows the relationship between v1 to v4 level and each duty ratio. table 14 lcd bias v1 v2 v3 v4 remarks 1/n (n-1)/n x v0 (n-1)/n x v0 2/n x v0 1/n x v0 n = 4 to 11
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 30 referece circuit examples [c1 = 1.0 to 4.7 [ m f], c2 = 0.1 to 0.47 [ m f]] when using internal regulator resistors when not using internal regulator resistors v ss c1 c1 c1 c1 c1 c1 + + + + + v dd intrs vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss c1 c1 c1 c1 c1 c1 + + + + + vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss rb ra c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 intrs figure 23 . when using a ll lcd power circuits (6-time v/c: o n , v/r: o n , v/f: o n ) when using internal regulator resistors when not using internal regulator resistors v ss + + + + + v dd vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss + + + + + vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 intrs intrs external power supply external power supply rb ra figure 24 . when using s ome lcd power circuits (v/c: o ff , v/r: o n , v/f: on )
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 31 v ss v dd intrs vout c5+ c3+ c1- c1+ c2+ c2- c4+ vr v0 v1 v2 v3 v4 external power supply + + + + + figure 25 . when using o nly voltage follower circuit (v/c: o ff , v/r: o ff , v/f: o n ) v dd intrs vout c5+ c3+ c1- c1+ c2+ c2- c4+ vr external power supply v0 v1 v2 v3 v4 figure 26 . when not using a ll lcd power circuits (v/c: o ff , v/r: o ff , v/f: o ff )
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 32 reset circuit setting resetb to " l " or reset instruction can initialize internal function. when resetb becomes " l " , following procedure is occurred. page address : 0 column address: 0 modify-read: off display on / off: off initial display line: 0 (first) initial com0 register: 0 (com0) partial display duty ratio: 1/81 reverse display on / off: off (normal) n-line inversion register: 0 (disable) entire display on / off: off (normal) power control register (vc, vr, vf) = (0, 0, 0) dc-dc step up: 3 times converter circuit = (0, 0) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) reference voltage control register: (ev5, ev4, ev3, ev2, ev1, ev0) = (1, 0, 0, 0, 0, 0) lcd bias ratio: 1/10 shl select: off (normal) adc select: off (normal) oscillator status: off power save mode: release when reset instruction is issued, following procedure is occurred. page address: 0 column address: 0 modify-read: off initial display line: 0 (first) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) reference voltage control register (ev5, ev4, ev3, ev2, ev1, ev0) = (1, 0, 0, 0, 0, 0) other instruction registers : not chaned while resetb is " l " or reset instruction is executed, no instruction except read status can be accepted. reset status appears at db4. after db4 becomes " l " , any instruction can be accepted. resetb must be connected to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb is essential before used.
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 33 instruction description table 15 . instruction table : don?t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description read display data 1 1 read data read data from ddram write display data 1 0 write data write data into ddram read status 0 1 busy adc on res 0 0 0 0 read the internal status set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 0 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb set modify-read 0 0 1 1 1 0 0 0 0 0 set modify-read mode reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode display on / off 0 0 1 0 1 0 1 1 1 d d = 0: display off d = 1: display on 0 0 0 1 0 0 0 0 set initial display line register 0 0 s6 s5 s4 s3 s2 s1 s0 2-byte i nstruction to specify the initial display line to realize vertical scrolling 0 0 0 1 0 0 0 1 set initial com0 register 0 0 c6 c5 c4 c3 c2 c1 c0 2-byte i nstruction to specify the initial com0 to realize window scrolling 0 0 0 1 0 0 1 0 set partial display duty ratio 0 0 d6 d5 d4 d3 d2 d1 d0 2-byte i nstruction to set partial display duty ratio 0 0 0 1 0 0 1 1 set n-line inversion 0 0 n4 n3 n2 n 1 n0 2-byte i nstruction to set n-line inversion register release n-line inversion 0 0 1 1 1 0 0 1 0 0 release n-line inversion mode reverse display on / off 0 0 1 0 1 0 0 1 1 rev rev = 0: normal display rev = 1: reverse display entire display on / off 0 0 1 0 1 0 0 1 0 eon eon = 0: normal display eon = 1: entire display on
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 34 table 1 6 . instruction table (continued) instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation select dc-dc step-up 0 0 0 1 1 0 0 1 dc1 dc0 select the step-up of the internal voltage converter select regulator resistor 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor 0 0 1 0 0 0 0 0 0 1 set electronic volume register 0 0 ev5 ev4 ev3 ev2 ev1 ev0 2-byte i nstruction to specify the electronic volume register select lcd bias 0 0 0 1 0 1 0 b2 b1 b0 select lcd bias shl select 0 0 1 1 0 0 shl com bi-directional selection shl = 0: normal direction shl = 1: reverse direction adc select 0 0 1 0 1 0 0 0 0 adc seg bi-directional selection adc = 0: normal direction adc = 1: reverse direction 1 1 1 0 1 0 0 0 set data direction & display data length(ddl) d7 d6 d5 d4 d3 d2 d1 d0 2-byte instruction to specify the number of data bytes(spi mode) . oscillator on start 0 0 1 0 1 0 1 0 1 1 start the built-in oscillator set power save mode 0 0 1 0 1 0 1 0 0 p p = 0: standby mode p = 1: sleep mode release power save mode 0 0 1 1 1 0 0 0 0 1 release power save mode reset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions nop 0 0 1 1 1 0 0 0 1 1 no operation test instruction 0 0 1 1 1 1 don't use this instruction.
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 35 read display data 8-bit data from d isplay d ata ram specified by the column address and page address can be read by this instruction. as the column address is incremented by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display d ata cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data write display data 8-bit data of display data from the microprocessor can be written to the ram location specified by the column address and page address. the column address is incremented by 1 automatically so that the microprocessor can continuously w rite data to the addressed page. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data d ata w rite s et co lumn a ddress s et p age address o ptional s tatus c olumn = co lumn +1 n o y es data w rite c ontinue ? d ummy d ata r ead s et c olumn a ddress s et p age a ddress o ptional s tatus c olumn = c olumn +1 n o y es d ata r ead c ontinue ? d ata r ead c olumn = c olumn +1 figure 27 . sequence for writing display data figure 28 . sequence for reading display data
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 36 read status indicates the internal status of the ks07 59 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on res 0 0 0 0 flag description busy the device is busy when internal operation or reset. any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being busy. adc indicates the relationship between ram column address and segment driver. 0: reverse direction (seg1 27 ? seg0), 1: normal direction (seg0 ? seg1 27 ) on indicates display on / off status. 0: display on, 1: display off res indicates the initialization is in progress by resetb signal. 0: chip is active, 1: chip is being reset. set page address sets the p age a ddress of display data ram from the microprocessor into the p age a ddress register. any ram data bit can be accessed when its p age ad dress and column address are specified. along with the column address, the p age a ddress defines the address of the display ram to write or read display data. changing the p age a ddress doesn't effect to the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 selected page description 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 : : : : : 1 0 0 1 9 accessible pages for displaying dot-matrix display data 1 0 1 0 10 accessible page for displaying icons 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 not accessible page. do not use these pages.
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 37 set column address sets the c olumn a ddress of display ram from the microprocessor into the column address register. along with the c olumn a ddress, the column address defines the address of the display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, c olumn a ddresses are automatically incremented. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 0 y6 y5 y4 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y6 y5 y4 y3 y2 y1 y0 selected column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 : : : : : : : : : : : : : : : : : : : : : : : : 1 1 1 1 1 0 1 1 25 1 1 1 1 1 1 0 1 26 1 1 1 1 1 1 1 1 27
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 38 set modify-read this instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the reset modify-read instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 reset modify-read this instruction cancels the modify-read mode, and makes the column address return to its initial value just before the set modify -r ead instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify- r ead reset modify- r ead set page address data p rocess n o y es change c omplete ? set column address (n) dummy r ead data r ead data w rite return c olumn a ddress (n) figure 29 . sequence for cursor display
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 39 display on / off turns the display on or off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d d = 1: display on d = 0: display off set initial display line register sets the line address of display ram to determine the initial display line using 2-byte instruction. the ram display data is displayed at the top row (com0) of lcd panel. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s6 s5 s4 s3 s2 s1 s0 s6 s5 s4 s3 s2 s1 s0 selected line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 0 1 0 0 0 0 80 1 0 1 0 0 0 1 81 1 0 1 0 0 1 0 : : : : : : : 1 1 1 1 1 1 1 no operation 2 nd i nstruction (2- b yte i nstruction for r egister s etting) setting i initial d isplay l ine e nd 1 st i nstruction (2- b yte i nstruction for m ode s etting) setting i nitial d isplay l ine s tart figure 30 . the sequence for setting the initial display line
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 40 set initial com0 register sets the initial row (com 0 ) of the lcd panel using the 2-byte instruction. by using this instruction, it is possible to realize the window moving without the change of display data. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 c6 c5 c4 c3 c2 c1 c0 c6 c5 c4 c3 c2 c1 c0 initial com0 0 0 0 0 0 0 0 com0 0 0 0 0 0 0 1 com1 0 0 0 0 0 1 0 com2 0 0 0 0 0 1 1 com3 : : : : : : : : 1 0 0 1 1 0 0 com76 1 0 0 1 1 0 1 com77 1 0 0 1 1 1 0 com78 1 0 0 1 1 1 1 com79 1 0 1 0 0 0 0 : : : : : : : 1 1 1 1 1 1 1 no operation 2 nd i nstruction ( i nitial com0 s etting) setting i nitial com0 e nd end 1 st i nstruction ( m ode s etting) setting i nitial com0 s tart figure 31 . sequence for setting the initial com0
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 41 set partial display duty ratio sets the duty ratio within range of 17 to 8 1 to realize partial display by using the 2-byte instruction. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 selected partial duty ratio 0 0 0 0 0 0 0 : : : : : : : 0 0 1 0 0 0 0 no operation 0 0 1 0 0 0 1 1/ 17 0 0 1 0 0 1 0 1/1 8 0 0 1 0 0 1 1 1/1 9 0 0 1 0 1 0 0 1/ 20 : : : : : : : : 1 0 0 1 1 1 0 1/78 1 0 0 1 1 1 1 1/79 1 0 1 0 0 0 0 1/80 1 0 1 0 0 0 1 1/81 1 0 1 0 0 1 0 : : : : : : : 1 1 1 1 1 1 1 no operation 2 nd i nstruction ( p artial d isplay d uty s etting) setting p artial d isplay e nd 1 st i nstruction ( m ode s etting) setting p artial d isplay s tart figure 32 . sequence for setting partial display
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 42 set n-line inversion register sets the inverted line number within range of 3 to 3 3 to improve the display quality by controlling the phase of the internal lcd ac signal ( internal m) by using the 2-byte instruction. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 n4 n3 n2 n1 n0 n4 n3 n2 n1 n0 selected n-line inversion 0 0 0 0 0 0-line inversion (frame inversion) 0 0 0 0 1 3-line inversion 0 0 0 1 0 4-line inversion : : : : : : 1 1 1 0 1 31-line inversion 1 1 1 1 0 32-line inversion 1 1 1 1 1 33-line inversion 2 nd i nstruction ( n -line i nversion s etting) setting n -line i nversion e nd 1 st i nstruction ( m ode s etting) setting n -line i nversion s tart figure 33 . sequence for setting partial display release n-line inversion returns to the frame inversion condition from the n-line inversion condition. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 1 0 0
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 43 reverse display on / off reverses the display status on lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ?1? ram bit data = ?0? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated entire display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this instruction has priority over the r everse d isplay on / off instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon ram bit data = ?1? ram bit data = ?0? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (entire) lcd pixel is illuminated lcd pixel is illuminated power control selects one of eight power circuit functions by using 3-bit register. an external power supply and part of internal power supply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off internal voltage converter circuit is on 0 1 internal voltage regulator circuit is off internal voltage regulator circuit is on 0 1 internal voltage follower circuit is off internal voltage follower circuit is on
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 44 select dc-dc step-up selects one of 4 dc-dc step-up to reduce the power consumption by this instruction. it is very useful to realize the partial display function. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 0 0 1 dc1 dc0 dc1 dc0 selected dc-dc converter circuit 0 0 3 times boosting circuit 0 1 4 times boosting circuit 1 0 5 times boosting circuit 1 1 6 times boosting circuit regulator resistor select selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power supply circuit. refer to table 13 . rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 [rb / ra] ratio 0 0 0 small 0 0 1 : : : : : 1 1 0 : 1 1 1 large
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 45 set electronic volume register consists of 2-byte instruction the 1 st instruction sets electronic volume mode, the 2 nd one updates the contents of electronic volume register. after second instruction, electronic volume mode is released. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 ev5 ev4 ev3 ev2 ev1 ev0 ev5 ev4 ev3 ev2 ev1 ev0 reference voltage ( a a ) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 2 nd i nstruction for r egister s etting setting e lectronic v olume e nd 1 st i nstruction for m ode s etting setting e lectronic v olume s tart figure 34 . sequence for setting the electronic volume
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 46 select lcd bias selects lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 1 0 b2 b1 b0 b2 b1 b0 selected lcd bias 0 0 0 1/4 0 0 1 1/5 0 1 0 1/6 0 1 1 1/7 1 0 0 1/8 1 0 1 1/9 1 1 0 1/10 1 1 1 1/11 shl select com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl shl = 0: normal direction (com0 ? com79) shl = 1: reverse direction (com79 ? com0) adc select changes the relationship between ram column address and segment driver. the direction of segment driver output pins c ould be reversed by software. this makes ic layout flexible in lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg0 ? seg1 27 ) adc = 1: reverse direction (seg1 27 ? seg0)
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 47 set data direction & display data length (3-pin spi mode) consists of two bytes instruction. this command is used in 3-pin spi mode only (ps0 = ? l ? and ps1 = ? l ? ) . it will be two continuous commands, the first byte control the data direction (write mode only) and inform the lcd driver the second byte will be number of data bytes will be write. when rs is not used, the display data length instruction is used to indicate that a specified number of display data bytes are to be transmitted. the next byte after the display data string is handled as command data. the 1 st instruction: set data direction (only write mode) rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x 1 1 1 0 1 0 0 0 the 2 nd instruction: set display data length (ddl) register rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x d7 d6 d5 d4 d3 d2 d1 d 0 d7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display data length 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 : : : : : : : : : 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 oscillator on start this instruction enables the built-in oscillator circuit. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 1 1 reset this instruction r esets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data ram. this instruction cannot initialize the lcd power supply, which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 48 power save the ks07 59 enters the power save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. set power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 0 p p = 0: standby mode p = 1: sleep mode release power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 1 release standby mode release sleep mode standby mode oscillator circuits: on lcd power supply circuits: off all com / seg output level: vss sleep mode oscillator circuits: off lcd power supply circuits: off all com / seg output level: vss set power save mode release power save mode figure 35 . power save routine n op non operation instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 1 test instruction this instruction is for testing ic. please do not use it. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 49 referential instruction setup flow: initializing with the built-in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power resetb pin = "h" user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for stabilizing the lcd power levels end of initialization figure 36 . initializing w ith the built- i n power supply circuits
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 50 referential instruction setup flow: initializing without the built-in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power set power save user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] regulator or follower register select [power control] waiting for stabilizing the lcd power levels end of initialization resetb pin = "h" release power save figure 37 . initializing w ithout the built- i n power supply circuits
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 51 referential instruction setup flow: data displaying end of initialization write display data by instruction [display data write] turn display on / off instruction [display on / off] end of data display display data ram addressing by instruction [initial display line] [set page address] [set column address] figure 38 . data displaying r eferential instruction setup flow: power off optional status power off (vdd-vss) end of power off set power save by instruction figure 39 . power o ff
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 52 referential instruction setup flow: partial duty changing start of partial changing set display off by internal instruction [display on / off] set partial duty by internal instructions [partial display duty ratio select] [initial display line register] [com0 register select] user lcd power setup by internal instructions [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for stabilizing the lcd power levels end of partial changing release power save set standby mode by internal instruction [power save mode] write display data & display on by internal instruction [display data write] [display on / off] waiting for discharging the lcd power levels figure 40 . partial duty changing note :1. partial com0 r egister s etting for com h/w half: [ 8 0 ? ( u ser d uty) ] / 2
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 53 specifications absolute maximum ratings table 16 . absolute maximum ratings (v ss = 0v) parameter symbol rating unit v dd - 0.3 ~ + 7.0 v v 0 , v out + 0.3 ~ + 17 .0 v supply voltage range v 1 , v 2 , v 3 , v 4 + 0.3 ~ v 0 v external reference voltage v ext +0.3 ~ v dd input voltage range v in - 0.3 ~ v dd + 0.3 v operating temperature range t opr - 40 ~ + 85 c storage temperature range t str - 55 ~ + 125 c notes: 1. vdd, v0, vout, v1 to v4, vext and vci are based on v ss = 0v. 2. voltage vout 3 v0 3 v1 3 v2 3 v3 3 v4 3 vss must always be satisfied. 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result.
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 54 dc characteristics table 17 . dc characteristics (v ss = 0v, v dd = 1 . 8 ~ 3 . 3 v, ta=-40~85 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 1 . 8 - 3 . 3 v v dd *1 operating voltage (2) v 0 4.0 - 1 5 .0 v v0, *2 high v ih 0. 7 v dd - v dd input voltage low v il v ss - 0. 3 v dd v *3 high v oh i oh = -0.5ma 0. 8 v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0. 2 v dd v *4 input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a *3 output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a *5 lcd driver on resistance r on ta = 25 c, v 0 = 8v - 2.0 3.0 k w segn comn *6 frame frequency f fr ta = 25 c 70 85 100 hz *7 table 18 . dc characteristics item symbol condition min. typ. max. unit pin used voltage converter circuit output voltage v out 3 / 4 / 5 / 6 voltage conversion (no-load ) 95 99 - % vout voltage regulator circuit operating voltage v out 5 . 4 - 1 5 .0 v vout voltage follower circuit operating voltage v 0 4.0 - 1 5 .0 v v0 * 8 reference voltage v ref ta = 25 c 2.04 2. 10 2. 1 6 v * 9
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 55 dynamic current consumption (1) when an external power supply is used. table 19 . dynamic current 1 (external power) (v dd = 3.0v, ta = 25 c) item symbol condition min typ max unit pin used v0-vss = 1 2 .0v, duty = 1/81 (display off) - - tbd m a *10 dynamic current consumption (1) i dd1 v0-vss = 1 2 .0v, duty = 1/81 (display on , checker pattern) - - tbd m a *10 dynamic current consumption (2) when the internal power supply is on table 20 . . dynamic current 2 (internal power) (v dd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used v0 - vss = 1 2 .0v, x 5 boosting, duty = 1/81, normal mode (display off) - - tbd m a *10 dynamic current consumption (2) i dd2 v0 - vss = 1 2 .0v, x 5 boosting, duty = 1/81, normal mode (display on , checker pattern) - - tbd m a * 10 current consumption during power save mode table 21 . power save mode current (v dd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used sleep mode current i dds1 during sleep - - 2 m a *10
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 56 table 22 . the relationship between oscillation frequency and frame frequency duty ratio item f cl f osc 1/n on-chip oscillator circuit is used f fr x n f fr x 4 x n (f osc : oscillation frequency, f cl : display clock frequency, f fr : frame frequency, n = 17 to 81) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is applied. *3 . cs1b, rs, db0 to db7, e_rd, rw_wr, resetb, ps1 , ps 0 , intrs, and ref *4 . db0 to db7 *5 . applies when the db0 to db7 pins are in high impedance. *6 . resistance value when -0.1[ma] is applied during the on status of the output pin segn or comn. ron [k w ] = d v[v] / 0.1[ma] ( d v : voltage change when -0.1[ma] is applied in the on status.) *7 . see table 22 for the relationship between oscillation frequency and frame frequency. *8 . the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range. *9 . on-chip reference voltage source of the voltage regulator circuit to adjust v0. *10 . applies to the case where the on-chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built-in power supply circuit is on or off. the current flowing through voltage regulation resistors(rb and ra) is not included. it does not include the current of the lcd panel capacity, wiring capacity, etc.
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 57 ac characteristics read / write characteristics (8080-series mp) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pwlw , t pwlr t cy80 t ah80 t as80 b0 to db7 ( write ) b0 to db7 ( read ) rd, /wr cs1b rs t pwhw , t pwhr figure 41 . read / write characteristics ( 8080-series mpu) table 23 (v dd = 1 . 8 ~ 3 . 3 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time t cy80 1000 - ns pulse width low for write pulse width high for write rw_wr (/wr) t pwlw t pwhw 12 0 12 0 - - ns pulse width low for read pulse width high for read e_rd (/rd) t pwlr t pwhr 24 0 12 0 - - ns data setup time data hold time t ds80 t dh80 8 0 30 - - ns read access time output disable time db0 to db7 t acc80 t od80 cl = 100 pf - 10 28 0 2 00 ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (t cy80 - t pwlw - t pwhw ) for write, (tr + tf) < (t cy80 - t pwlr - t pwhr ) for read
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 58 read / write characteristics (6800-series microprocessor) t dh68 t od68 t ds68 t acc68 0.1v dd 0.9v dd t ewhw , t ewhr t cy68 t ah68 t as68 db0 to db7 ( write ) db0 to db7 ( read ) e cs1b rs, r/w t ewlw , t ewlr figure 42 . read / write characteristics (6800-series microprocessor) table 24 (v dd = 1 . 8 ~ 3 . 3 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs rw t as68 t ah68 0 0 - - ns system cycle time t cy68 1000 - ns enable width high for write enable width low for write e_rd (e) t ewhw t ewlw 12 0 12 0 - - ns enable width high for read enable width low for read e_rd (e) t ewhr t ewlr 24 0 12 0 - - ns data setup time data hold time t ds68 t dh68 8 0 30 - - ns read access time output disable time db0 to db7 t acc68 t od68 c l = 100 pf - 10 28 0 2 00 ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tcy68 - tewhw - tewlw ) for write, (tr + tf) < (tcy68 - tewhr - tewlr ) for read
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 59 serial interface characteristics db7 ( sid ) db6 ( sclk ) rs cs1b t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 43 table 25 (v dd = 1 . 8 ~ 3 . 3 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) ts cy ts hw ts lw 1 50 60 60 - - - ns address setup time address hold time rs t ass t ahs 6 0 6 0 - - ns data setup time data hold time db7 (sid) t dss t dhs 6 0 6 0 - - ns cs1b setup time cs1b hold time cs1b t css t chs 6 0 6 0 - - ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 60 reset input timing resetb internal status t rw t r reset complete during reset figure 44 table 26 (v dd = 1 . 8 ~ 3 . 3 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit reset low pulse width resetb t rw 2 000 - ns reset time - t r - 2 000 ns
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 61 reference applications microprocessor interface in case of interfacing with 6800-series (ps 0 = " h ", ps1 = "h") 6800-series mpu cs1b rs e_rd rw_wr db0 to db7 resetb ps0 ps1 KS0759 db0 to db7 resetb v dd v dd rw e rs cs1b figure 45 . interfacing with 6800-series in case of interfacing with 8080-series (ps 0 = " h " , ps1 = "l" ) 6800-series mpu cs1b rs e_rd rw_wr db0 to db7 resetb ps0 ps1 KS0759 db0 to db7 resetb v ss v dd wr /rd rs cs1b figure 46 . interfacing with 8080-series
81 com / 1 28 seg driver & controller for stn lcd preliminary spec. ver. 0 . 2 ks07 59 62 in case of serial peripheral interface with rs pin (ps0 = "l" , ps1 = " h " ) mpu ps0 ps1 KS0759 v dd v ss db0 to db5 open cs1b cs1b rs rs resetb resetb db6(sclk) sclk db7(sid) sid figure 47 . serial interface in case of serial peripheral interface with software command (ps0 = "l" , ps1 = "l" ) mpu ps0 ps1 KS0759 v ss v ss db0 to db5 open cs1b cs1b rs vss/vdd resetb resetb db6(sclk) sclk db7(sid) sid figure 48 . serial interface
ks07 59 preliminary spec. ver. 0 . 2 81 com / 128 seg driver & controller for stn lcd 63 connections between ks07 59 and lcd panel single chip configurations (1/81 duty) com39 - com0 coms coms com 79 - com 40 seg 127 seg 126 ? seg1 seg0 KS0759 ( bottom view ) com 39 - com0 coms coms com 79 - com4 0 seg0 seg1 ? seg 126 seg 127 KS0759 ( top view ) ? a x a ? a x a 8 0 12 8 pixels ? a x a ? a x a 8 0 12 8 pixels figure 49 . shl = 0, adc = 1 figure 50 . shl = 0, adc = 0 com40 com 79 coms coms com0 com 39 seg 127 seg 126 ? seg1 seg0 KS0759 (top view) coms com0 com 39 com4 0 com 79 coms seg0 seg1 ? seg 126 seg 127 KS0759 (bottom view) ? a x a ? a x a 8 0 12 8 pixels ? a x a ? a x a 8 0 12 8 pixels figure 51 . shl = 1, adc = 0 figure 52 . shl = 1, adc = 1

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